1. Field of the Invention
The invention relates to an electrically rewritable non-volatile semiconductor memory device (EEPROM), such as a flash memory, and a reading-out method thereof.
2. Description of the Related Art
A highly integrated NAND-type non-volatile semiconductor memory device which connects a plurality of memory cell transistors (hereinafter referred to as memory cells) to and between bit lines and source lines in series to form a NAND string is well known in the art.
In a common NAND-type non-volatile semiconductor memory device, when erasing, a high voltage, such as 20V, is applied to a semiconductor substrate and 0V is applied to a word line. As such, electrons are pulled out from a floating gate, i.e., a charge accumulation layer formed by poly-silicon material etc., and a threshold voltage is lower than an erasing threshold voltage (for example, −3V). In addition, when performing write-in (programming), 0V is applied to the semiconductor substrate, and a high voltage, such as 20V, is applied to a control gate. As a result, electrons are injected from the semiconductor substrate into the floating gate, thereby making a threshold voltage higher than a write-in threshold voltage (for example, 1V). States of a memory cell which utilizes the threshold voltages may be determined by applying a readout voltage (for example, 0V) between the write-in threshold voltage and a readout threshold voltage to the control gate to determine whether a current is flowing through the memory cell.
FIG. 18 illustrates a configuration example of an EEPROM according to the first conventional example disclosed in Patent Document 1. In FIG. 18, a memory chip 100 and a controller 160 are illustrated. The memory chip 100 comprises a memory cell array 101 connected to a row decoder circuitry 111 and a column decoder circuitry 113. A reading-out circuitry 121 comprises a sense amplifier and any other relevant circuitry. The output of the reading-out circuitry 121 is supplied to a set of registers. A bus 130 connecting the memory chip 100 to the controller 160 transfers data and addresses, commands, parameters, and so on between the controller 160 and the memory chip 100. Here, an example in which the composite value of the read-out data is formed in the memory chip 100 and then passed to the controller to be output to a host is shown. In FIG. 18, an averaging circuit of the read-out data is shown. The averaging circuit, consisting of an accumulator 123 and a divider 129, calculates a mean based on individual read-out data by the accumulator and the divider.